1. Field of the Invention
The present invention generally relates to the manufacture of field effect transistors and, more particularly, to the development of desired conduction/cut-off voltage in sub-micron field effect transistors.
2. Description of the Prior Art
Field effect transistors have become the active electronic element of choice for the majority of digital electronic circuits formed at small size and high integration density. The basic principle of operation of field effect transistors is to use a voltage applied to a gate electrode insulated from the conduction channel of the device to develop an electric field which controls the population of carriers in a body of semiconductor material which forms the conduction channel of the device. The simplicity of the structure forming a field effect transistor leads to high manufacturing yields and relatively lower process costs. Further, device simplicity allows device fabrication at extremely small sizes, allowing improvement in signal propagation time, noise immunity, load capacitance and other electrical parameters as well as substantial flexibility in device and isolation structure design and economy of fabrication since more circuits may be formed on a single wafer or chip.
Additionally, the simplicity of field effect transistor geometries allows the transistors to be tailored to many specific purposes and applications. For example, low thresholds and increased on-currents can be developed by doping of the conduction channel. Alternatively, thresholds may be maintained at higher levels in, for example, dynamic memory arrays. Short channel effects can be largely avoided by so-called lightly doped drain structures, and the like.
However, the electrical field developed within the conduction channel may not be uniform, particularly at the lateral edges (generally referred to as "corners") of the conduction channel which generally coincides with the periphery of the gate electrode. The conduction characteristics at the corners of the channel (referred to hereinafter as corner conduction) may therefore be quite different from those of the central portion of the channel (referred to hereinafter simply as channel conduction). Therefore, a rigorous analysis of a field effect transistor would include an equivalent circuit of two parallel-connected field effect transistors having different conduction/cut-off thresholds.
The planar or channel portion of the transistor generally dominates the on-current characteristics of the transistor and, in relatively larger (e.g. wider channel) devices, the field can be considered as relatively uniform throughout the conduction channel. Consequently, device characteristics, such as conduction/cut-off threshold Vt, of particular interest in digital circuits, are highly predictable. However, so-called off-current occurs principally in the corners of the conduction channel, even in wide devices, and, in practical effect (particularly for digital devices) appears as a different conduction/cut-off threshold voltage. Conduction in the corners of the channel may also contribute significantly to the on-current of the transistor, as is exploited in so-called multi-mesa transistor designs.
As field effect transistors are made smaller, the conduction effects at the corners of the conduction channel become relatively more significant and, in fact, may become dominant at sub-micron channel widths. The practical effect of corner conduction as it becomes comparable to channel conduction is to relatively increase the off-current of the transistor while providing some increase in on-current or to "soften" the conduction characteristic near the cut-off voltage. If corner conduction is dominant, the effect is an increased conduction/cut-off threshold, V.sub.t.
Additionally, increased variance of conduction/cut-off threshold has been observed as device size decreases in the sub-micron regime where very small differences in channel dimensions may greatly affect the relative contributions of corner and channel conduction of transistors. While threshold voltages will generally be quite uniform across a wafer or chip for transistors of a similar size (although more critical at smaller sizes) it is common for complementary transistors (e.g. CMOS) to be fabricated at different sizes to increase symmetry of conduction currents and different thresholds developed from differences in transistor size may severely compromise the intended switching symmetry in a manner which is somewhat unpredictable and not readily correctable in device design or fabrication.
Particularly for application to digital circuits and low power CMOS logic, it is desirable to minimize off-current while maximizing on-current. As the off-current effects increase with increasing corner conduction contribution, the ratio of on-current to off-current is reduced. Further, differing thresholds between interconnected chips may effectively decrease operating margins. "Softening" of the cut-off characteristic near the threshold voltage, V.sub.t, and/or increase of the threshold voltage is also particularly undesirable in digital circuits.
Since the corner conduction results from non-uniformity of the electric field within the channel, it may be possible to adjust the electric field by performing an angled impurity implantation in the conduction channel region. However, implantation causes crystal lattice defects in the semiconductor material which cannot be fully repaired by annealing consistent with the adjustment of electrical field which would be necessary. Normal channel conduction characteristics may also be altered by impurity implantation. Angled implantation is also a complex and difficult process which is likely to result in some degree of non-uniformity between devices, even as formed on the same wafer. For these and a variety of related reasons, manufacturing yield is relatively reduced when angled implantation is employed. In any event, it is not clear that angled implantation would provide a suitable adjustment of electric field within the conduction channel, particularly as channel width is reduced.